Random Access Memory (RAM) is a significant computer system element in which data is stored and retrieved. Heretofore DRAMs (Dynamic Random Access Memories) have constituted most of RAMs. DRAMs are integrated circuits which have the most data packing density with a single memory cell formed by a transistor and a capacitor, often termed 1T1C in abbreviated fashion.
But DRAM technology is nearing its end with the continuing shrinkage of feature dimensions and an emerging technology is thyristor-based memory cell RAMs. At very small dimensions, thyristor memory cell arrays have many advantages over DRAM memory cell arrays, including less power consumption and scalability for further shrinkage. As in the case of DRAMs, it is highly desirable that data be transferred at high-speed to and from thyristor memory cell array RAMs.
DDR provides a pathway in adapting thyristor memory cell RAMs to move data stored in a RAM memory cell array and of writing bit information into a RAM memory cell array for storage at high speed. A long-accepted standard for DRAM, DDR SDRAM (Double Data Rate Synchronous DRAM) standard, or more precisely, a series of standards, developed by JEDEC (Joint Electron Device Engineering Council), defines how bits are transferred to and from DRAM integrated circuits. The DDR SRAM (or DDR for short) standard also defines high speed transfer of bits to and from memory modules of DRAM integrated circuits along the buses of a computer system.
One approach toward adapting thyristor memory cell arrays to be compatible with DDR standards, specifically LPDDR4, is described in U.S. patent application Ser. No. 15/729,627, filed Oct. 10, 2017, entitled “DDR Controller for Thyristor Memory Cell Arrays,” and assigned to the present assignee. Such direct approaches, more or less, of adapting the thyristor memory cell arrays to DDR standards have the advantage of the possibility of a straight-forward substitution of DDR DRAMs with thyristor memory cell RAMs or substitution with relatively minor changes. Nonetheless, thyristor memory cell arrays have different requirements than DRAMs and under certain circumstances problems may arise.
The present invention addresses these issues by another approach to DDR constraints for a robust mechanism for the high-speed transfer of data to and from thyristor memory cell arrays.